Power integrated circuits (PICs) find application in an increasingly wide variety of electronic devices. Typically,. PlCs comprise one or more high-voltage field effect transistors (HVFETs) having a device structure such as those disclosed in U.S. Pat. No. 6,207,994 (“the '994 patent”), which is herein incorporated by reference. Each of the devices disclosed in the '994 patent has a source region and a drain region separated by an intermediate region. A gate structure is disposed over a thin oxide layer over the metal-oxide-semiconductor (MOS) channel of the device. In the on state, a voltage is applied to the gate to cause a conduction channel to form between the source and drain regions, thereby allowing current to flow through the device. In the off state, the voltage on the gate is sufficiently low such that no conduction channel is formed in the substrate, and thus no current flow occurs. In this condition, high voltage is supported between the drain and source regions.
Most power integrated circuits (ICs) contain one or more output HVFETs that control current flow through one or more external loads. By way of example, FIG. 7 of the '994 patent discloses an HVFET structure with interdigitated source and drain regions that is commonly utilized as an output transistor in many types of power devices. In the design of a particular PIC, these elongated source/drain segments may be replicated to increase the current handling capability of the power device.
FIG. 1 shows a typical prior art PIC fabricated on a semiconductor die 10 having an aspect ratio defined as the ratio of the length (L) to the width (W). Included on semiconductor die 10 is a control circuit 11 that is utilized to control on/off switching of an output HVFET 12. In PIC designs, it is customary to utilize a single standardized control circuit design coupled to a variety of HVFET layouts of differing sizes (e.g., number of segments) to create a family of devices with similar functionality, but with differing current handling capability. For example a family of PICs, each with differing current handling capabilities, may be created by increasing the number of parallel segments of HVFET 12. According to this traditional approach, PICs with larger current handling capability have a larger width (W) to accommodate more source/drain segments, but the same length (L). In other words, in prior art PIC designs, the length of the output HVFET 12 is substantially constant, and equal to the length of control circuit 11. PIC devices with more current handling capability have more segments added in parallel, which increases the width of the semiconductor die.
To achieve maximum utilization of the package space that houses semiconductor die 10, control circuit 11 is usually designed with a length that is much larger than its width. In a typical PIC product family the smallest device is designed to be long and narrow (i.e., large aspect ratio), with larger devices having an increased width dimension due to the added number of HVFET segments (i.e., smaller aspect ratio). That is, the aspect ratio of larger devices decreases as more segments are added.
Aspect ratio is a critical parameter in the design of a monolithic PIC. A PIC fabricated on a semiconductor die having a very large or very small aspect ratio often suffers from mechanical stress caused by the molding compound used to bond the die to the package. This stress can adversely change the electrical properties of the PIC circuitry. A semiconductor die having a length that is substantially equal to its width (i.e., aspect ratio=1) minimizes stress and permits more efficient wire routing of the control circuit. The difficulty, however, is that HVFET 12 is required to have elongated segments in order to achieve a specific current handling capability. The package also has maximum cavity size. Thus, while it is desirable to manufacture a PIC on a semiconductor die having a substantially square shape, the need to provide a product family with a range of current handling capabilities which fits within a package cavity size has constrained the dimensions of control circuit 11 and semiconductor die 10.
The solution of the prior art has been to provide a control circuit that has a relatively narrow width and a much larger length that is substantially equal to the maximum package cavity size. For example, in FIG. 1 the length of control circuit 11 is about four times its width. However, this causes inefficiencies in control circuit wiring. Another significant shortcoming of this prior art approach is that PIC devices with small HVFETs (fewer segments) suffer from package stress problems caused by high semiconductor die aspect ratio.
Thus, there is an unsatisfied need for an improved monolithic PIC design that overcomes the problems of poor control circuit area efficiency and high PIC aspect ratio.